CPES Power Management Consortium (PMC)
Focused research is designed to address specific research issues pertaining to CPES core research endeavors. The program allows multiple companies to pool together financial resources and technical support in a synergistic manner so that specific research agendas and technical barriers can be penetrated in a timely manner. There is currently one mini-consortium, Power Management Consortium (PMC), which is sponsoring research in developing voltage regulator modules to address power management issues for the next generation of microprocessors.
The new generation of Intel's microprocessor is operating at a much lower voltage and higher current, with a fast dynamic response in order to implement the sleep/power mode of operation. This particular mode of operation is necessary to conserve energy, as well as to extend the operation time for any battery-operated equipment. The challenge for the voltage regulator module in this case is to provide a precisely regulated output with fast dynamic response in order to transfer energy as fast as possible to the microprocessor.
At the request of Intel, CPES established a mini-consortium to address the issue of power management for future generations of microprocessors, targeting at sub-1 volt and 100-200 amps current. As a result of this focused research, the CPES team has developed a multi-phased voltage regulator module. Instead of paralleling power semiconductor devices in order to meet the current demand and efficiency requirements, the research team has proposed to parallel a number of mini-converters. By paralleling the mini-converters and phase-shifting the clock signal, not only we were able to cancel the significant part of the output current ripple, but also to increase the ripple frequency by N time, where N is the number of channels we parallel. This has resulted in demonstrated improvement, specifically, 4 times improvement in transient response, 10 times reduction in output filter inductors, 6 times reduction in output capacitors, 6 times improvement in power density, and 3 times improvement in profile.
Today, every Intel processor is powered by such multi-phased VRMs developed by CPES. CPES researchers are continuing to conduct research in this particular subject by exploring new topologies in power semiconductor devices, magnetics, and integrated packaging concepts in order to improve the transient response and minimize the I2R loss due to continuous reduction in voltage as well as continuous increase in load current. We are currently exploring a range of input voltages in VRM technologies, from 12V up to 48V, to accomplish this objective.