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Design of GaN-based MHz Totem-pole PFC Rectifier

Image of prototype of interleaved 1.2kW MHz totem-pole PFC
Fig. 1. Prototype of interleaved 1.2kW MHz totem-pole PFC
With the advent of 600V gallium-nitride (GaN) power semiconductor devices, the totem-pole bridgeless power factor correction (PFC) rectifier, which was a nearly abandoned topology, has suddenly become a popular solution for applications like front-end converters in server and telecommunication power supplies. This is mostly attributed to the significant performance improvement of the GaN high-electron-mobility transistor (HEMT). When compared to the silicon (Si) metal - oxide - semiconductor field-effect transistor (MOSFET), particularly it has s better figure-of-merit and a significantly smaller body diode reverse-recovery effect.

The cascode GaN HEMT is applied in the totem-pole PFC rectifier while pushing the operating frequency to above 1MHz. Several important issues, which are less significant at low frequencies, are emphasized at high frequencies, and corresponding solutions are proposed and experimentally verified.


In this research, the advantages of the totem-pole PFC rectifier are summarized at first, while the differences between hard-switching and soft-switching and between the Si MOSFET, and the GaN HEMT are illustrated in second. After that, detailed design considerations are presented, including the ZVS extension to solve the problem of switching loss caused by non-ZVS valley switching; variable on-time control to improve the power factor, particularly the zero-crossing distortion caused by traditional constant on-time control; and interleaving control to cancel the input current ripple. The volume of the DM filter is reduced significantly by pushing the operating frequency to several MHz and the use of multi-phase interleaving.

A 1.2kW two phase interleaved totem-pole PFC prototype is demonstrated with 220W/in3 power density and 99% efficiency. All proposed functions with closed-loop control are implemented by a 120MHz MCU.


Image of tested efficiency curve
Fig. 2. Tested efficiency
Image of MCU-based digital control implementation
Fig. 3. MCU-based digital control implementation
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