New SBIR-STTR Supplemental Award enables research collaboration on High-Temperature Packaging
CPES has been pursuing technologies that would increase the operating temperature of its integrated power electronic modules (IPEM) beyond 250°C. Thanks to the National Science Foundation Engineering Research Centers (NSF ERC) Small Business Innovation Research/Small Business Technology Transfer (SBIR/STTR) Phase II supplemental funding opportunity for collaborative research, CPES has teamed with Advanced Thermal Technologies (ATT) to conduct research on "Thermally-Efficient, Mechanically-Reliable Packaging of High-Temperature Power Semiconductor". IPEMs serve as building blocks for power electronic systems. Currently, overall thermal management is not an integrated part of the Center's low-temperature package, i.e., a die is attached to an aluminum heat sink via layers of copper, ceramic, solder, and thermal grease, as in Fig. 1 (a). These thermal layers constitute an inefficient heat conduit unsuitable for high-temperature applications. The mismatch among the coefficients of thermal expansion (CTE) of the layers leads to premature failure during temperature cycling. Thus, a thermally efficient, mechanically reliable high-temperature packaging paradigm is being sought that leverages state-of-the-art thermal management materials and packaging processes. In particular, CPES needs a CTE-matched, isolated, solderable heat sink (CMISHS) to which dice or solderable modules can be directly bonded, as shown in Fig. 1 (b), eliminating a majority of the thermal/packaging layers.
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