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Point-of-Load Conversion
The aggressive Intel roadmaps for the future generations of microprocessors and their chipsets have imposed a number of severe challenges on the issues of power delivery and power management. Responding to Intel’s microprocessor challenges, the CPES team developed a multi-phase VRM module based on paralleling multiple buck converter cells in 1997. This new multi-phase VRM has been adopted by the entire industry as standard practice since 1998. Today, every computer containing the Intel microprocessors uses the multiphase VRM approach developed at CPES. Future VRs, that are for serving not only the microprocessor but also for serving other loads such as GPS, cell phones, PDAs, and other portable electronics, must be designed with significantly increased output current, faster transient response, lower output voltage, and tighter output voltage regulation. To meet these stringent requirements, the current practice demands a significant increase in the output capacitors and decoupling capacitors. This is not acceptable either from the cost point of view or from the limited motherboard real estate point of view. Aiming at more cost-effectiveness, higher power density, and more efficient power management solutions, researchers at CPES have been investigating alternative power system architectures, control methods, power conversion, topologies, packaging, more integration, and improved thermal management solutions. The latest Point of Load (POL) technology developed at CPES uses novel packaging called “Stacked Power” that allows for active devices to be embedded inside a ceramic layer of high thermal conductivity. This in turn frees up the top and bottom sides for the integration of other circuit parts. This vertical integration allows for layouts with low circuit parasitics so that efficient high-frequency operation can be realized. The passives are integrated with the active layer by means of Low-Temperature Co-fired Ceramic (LTCC). LTCC technology enables the integration of low-profile inductors with high current capabilities. The 3D integrated solution enables the integration of bulky magnetics components in the form of a low profile substrate upon which the active components can be integrated. Further reduction of magnetics was demonstrated by employing negatively coupled inductors, a technique proposed in 1998. Related CPES Research Volumes: |
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